CAEN V265

 

Set the VME Address

The Model V 265 is a 8 channel charge integrating ADC. For each channel, the input charge is converted to a voltage level by a Charge to Voltage Converter (CVC). The conversion process begins whenever a GATE input signal (NIM level) becomes TRUE, and it stops when the GATE signal becomes FALSE.  As soon as the GATE becomes FALSE, each CVC output voltage is sequentially transformed to a 16-bit word by two parallel 12-bit Analog to Digital Converters (ADC), and at the same time a BUSY output signal is available at the corresponding front panel connector. During the time interval in which the BUSY signal is active no GATE signal is accepted.


Please refer to the manual for more details.

 

V265 Data Record format

The ADC data from the V265 can be in either the short or the long form. The short form will be used whenever possible, but analysis programs must be prepared to handle either form.


Short Form:

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^--------------------------------- V265 ID (from header)

--------^-^^^--------------------------- Crate number

-------------^-^^^^--------------------- Card number

--------------------^^^----------------- Channel number

-----------------------^---------------- Range Type (0==12 bit, 1==15bit)

-------------------------^^^^ ^^^^ ^^^^- adc value


Long Form:

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^----------------------- V265 ID (from header)

-----------------^^ ^^^^ ^^^^ ^^^^ ^^^^- length (always 2 longs)

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

--------^-^^^--------------------------- Crate number

-------------^-^^^^--------------------- Card number

--------------------^^^----------------- Channel number

-----------------------^---------------- Range Type (0==12 bit, 1==15bit)

-------------------------^^^^ ^^^^ ^^^^- adc value

Force ALL/NONE of the channels to be enabled

Option to exclude ADC values that are zero from the data stream

ADC values from channels that are not enabled will be dumped and not included in the data stream.

Force a Gate signal

Reset the board and clear the FIFO