ANL Gretina4 (MJD)

This is a 8-channel, 12-bit signal processing board which continuously samples at a rate of 100 MHz. The board was also designed to meet the more general requirements for a signal processor board as specified by the Argonne workshop on digital electronics (2001) for low-energy nuclear physics experiments. This board is differs from most commercial digitizers in that it emulates, in a single large FPGA, much of the functionality found in analog systems for Ge detectors.

See the Gretina4Manual.pdf for more specific information about the original card and Gretina4AManual.pdf for details of the new version.

Firmware

The newest version of the VME firmware is available here: ANL_VME.mcs.

The main firmware is available here: 20161222_MJD_MSTR_digitizer.bin.

Download the lab tools from here:

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/v2012_4---14_4.html

• Connect the Platform Cable to the JTAG header on the Gretina card and to a computer with the Lab Tools installed . Put the card in a VME crate and power it on.
• Start the Xilinx iMpact software, open a boundary scan, and initialize the data chain. iMpact should detect the Platform cable and two chips.
• Right-click on the image of the chip labeled xcf02s. This is the VME FPGA. Click the 'assign new configuration file' option and select VME firmware file. Right-click on the image of the chip and click 'program'.
• When the programming is complete, power-cycle the crate. You are now running the new VME firmware.
• In the ORCA GRETINA dialog, select the ‘Firmware’ tab and download the main FPGA .bin file that is available above. A bug in ORCA causes the process to hang after the verify process. Just click the ‘STOP’ button when the verify is finished.
• NOTE: if there are problems loading the firmware, see the bottom of this page for more info.

User Dialog

Parameters common to all channels

Threshold and triggering parameters

Write all values to the hardware

Helpful Hint.

Use Cmd-Shift-> and Cmd-Shift-< to make this dialog control a card in a slot to the right or left of the currently selected card.

Use Cmd-C to bring up another card dialog, set one of them to the Rates display and one to the Settings display to see rates while setting thresholds.

Flags for pile-up control

Rate over time.

Current FIFO state information

Channel-by-channel rates. Note that you can enable/disable channels here also

Waveform record

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^----------------------- Data ID (from header)

-----------------^^ ^^^^ ^^^^ ^^^^ ^^^^- length

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

--------^-^^^--------------------------- Crate number

-------------^-^^^^--------------------- Card number

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^ always 0xAAAAAAAA

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^--------------------------------- Geo address

^^^ ^^^^ ^^^^-------------------- Packet length including header

^^^^ ^^^^ ^^^^---- User Defined

^^^^ Channel

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Time Stamp of Discriminator Firing (31:0)

xxxx xxxx x000 xxxx xxxx xxxx xxxx xxxx

^^^^ ^^-------------------------------- Header Length

^^ ^---------------------------- Event Type

^^^^-------------------- Header Type

^^^^ ^^^^ ^^^^ ^^^^ Time Stamp of Discriminator Firing (47:32)

xxxx xxxx xxxx xxxx xxxx 0xxx 0xx0 0000

^^^^ ^^^^ ^^^^ ^^^^---------------------Time Stamp of previous Discriminator Firing (15:0)

^^^^--------------- PU,PO,GE,SE

^^^---------- OF,PV,ED

^^------ VF,WF

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^-Time Stamp of previous Discriminator Firing (47:16)

0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^-Sampled baseline bits 23:0

0000 0000 0000 0000 0000 0000 0000 0000

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ------------------------------Post-rise sum (7:0)

^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^-Pre-rise sum (23:0)

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^^^---------------------Timestamp of peak detect (15:0)

^^^^ ^^^^ ^^^^ ^^^^-Post-rise sum (28:8)

xxxx xxxx xxxx xxxx 00xx xxxx xxxx xxxx

^^^^ ^^^^ ^^^^ ^^^^---------------------Timestamp of trigger(15:0)

^^ ^^^^ ^^^^ ^^^^-Last post-rise sum 23:8

00xx xxxx xxxx xxxx 00xx xxxx xxxx xxxx

^^ ^^^^ ^^^^ ^^^^---------------------Last post-rise leave sample

^^ ^^^^ ^^^^ ^^^^-post-rise leave sample

00xx xxxx xxxx xxxx 00xx xxxx xxxx xxxx

^^ ^^^^ ^^^^ ^^^^----------------------pre-rise enter sample

^^ ^^^^ ^^^^ ^^^^-pre-rise leave sample

00xx xxxx xxxx xxxx 00xx xxxx xxxx xxxx

^^ ^^^^ ^^^^ ^^^^----------------------base sample

^^ ^^^^ ^^^^ ^^^^-peak sample

^^^^ ^^^^ ^^^^ ^^^^--------------------- First Data Word

....N Long Words of Raw data points follow.....

Recovering from Firmware Problems

If the GRETINA cards are not working properly and all of the lights on the front of the card are yellow, you will have to try to reinstall the firmware or change the fuses on the board. If the card is completely unresponsive you may have to go back to the oldest VME and FPGA firmware to recover. See the GRETINA4M page for details.

Additional Notes:

· Turning off the VME crate will erase the main FPGA firmware you installed using XILINX but not the main FPGA firmware you installed using ORCA.

· None of these steps should take more than 10-20 minutes; if ORCA is taking forever to load the main FPGA firmware something may be wrong.

· The GRETINA card must be plugged into a powered VME crate for the XILINX software to read it and install firmware on it.

Various event related counters

Data pipeline delay values

Default values should result in the card triggering on a reasonable input signal. But this is a complex card. See the manual for full details